The present invention relates to a reconfigurable logic device.
Reconfigurable (programmable or writable) semiconductor devices such as field-programmable gate arrays (FPGAs) are widely used because of the flexibility provided by their rewritability (e.g. JP 2002-538652T).
A common island style FPGA is composed of logic-element configurable logic blocks (CLBs), switch elements SB and CB, and input/output elements IOB.
The logic element CLB is a programmable element that creates a combinational circuit, and each CLB is formed of a data flip-flop (DFF), a look-up table (LUT), etc. In a k-input LUT (k-LUT), 2 raised to the k-th power of static random access memory (SRAM) cells are used, and a function with k variables is created, such as a system in which the truth table of any logic function is retained in the SRAM and output is performed by referencing the truth table according to the input.
In order to bring about a signal path between CLBs linking the logic function portions, the switch elements CB and SB capable of switching the signal path are placed between the CLBs. The switch element CB is an element that switches between a logic block LB and a wiring channel, and the switch element SB is an element that switches between vertical and horizontal wirings in a portion where the vertical and horizontal wirings cross.
The input/output element IOB is a component that plays the role of an interface between the input/output of the device and the logic block LB.
The present applicant or the present inventors have developed an “MPLD™ (Memory-based Programmable Logic Device)” that creates a circuit configuration by means of memory cell units. The MPLD is illustrated in, for example, WO 2007/060763. The MPLD interconnects memory arrays called multi look-up tables (MLUTs). The MLUT stores truth value data, and forms a wiring circuit and a logic circuit. The MPLD has achieved a function almost equivalent to the FPGA by arranging these MLUTs in an array configuration and interconnecting them. The MPLD is a device enabling a flexible logic area and wiring area by using the MLUT as both a logic circuit and a wiring circuit by means of truth table data (e.g. WO 2007/060763), and is different from the FPGA, which includes a dedicated switching circuit for the connection between memory cell units.
WO 2014/163099 discloses an MLUT 30 in which a reconfigurable logic multiplexer 50 is used for data input/output and truth value data is used for the select control signal of the reconfigurable logic multiplexer 50. In the Example, an ATD circuit 200 is used for the synchronization/asynchronization of the MLUT.